The invention relates to a three cycle bus arbiter which operates in a polling-transfer-confirmation system bus environment and more particularly, relates to a bus arbiter which provides advance transfer signals to an intersystem bus link during the same bus cycle in which it provides request/grant operations for a system bus unit.
It is well known to those skilled in the art of computer design as well as to users of digital computer systems that generally more speed in computation and information processing is nearly always desirable if it can be provided in an economical manner. One way in which the speed of processing may be increased for a digital computer is by increasing the number of instructions or floating point operations which may be performed per second by the system. One school of thought holds that the manner in which this is done is by decreasing the cycle time for a very powerful processor so that a single processor may execute more instructions or perform more floating point operations per second. While this option is often attractive and relatively straightforward from an engineering standpoint, it is also quite expensive in that it requires that a given system employ the most powerful and advanced subsystems and circuitry available to those skilled in the art at the time that the system is being designed. This entails some risk since the underlying technology may be relatively new and untried and may prove to be inoperable in the environment of a very high performance digital computer.
As an alternative, it is sometimes desirable to employ multiple processing units or even multiple digital computers connected together to share information. It is well known to those skilled in the art, that once multiple processors begin sharing information among themselves, careful design must be employed in order to insure that the number of cycles required to transfer information from one processor to another or among storage units does not increase to the point that the multiple processor system is only marginally faster than a single processor system.
One of the problems associated with multiple processor systems is that typically, a customer is forced to purchase a system with a fixed number of processors. That is, a particular system will be optimized to use two, four or eight processors and if the customer desires to have certain of the processors removed in order to satisfy somewhat lesser performance requirements, while reducing the cost of the system, it is often necessary that he purchase extraneous hardware which stands idle since it would normally be used to handle tasks for the maximum number of processors for which the system is configured.
What is needed then, is a digital computer and in particular, a bus arbitration system for a digital computer which is economically configurable for one or a plurality of processors and which reduces the number of processor or bus cycles required to transfer information from one system bus to another system bus in a multiple system bus, multiple processor digital computer system.